OV5640 Module - Mind Instrument

OV5640 Camera Module

Introduction

ov5460 left top 网页用图

ov5460 left bottom 网页用图

ov5460 right top 网页用图

ov5460 right bottom 网页用图

ov5460 双目组合1 网页用图

ov5460 双目组合2 网页用图

ov5460 left top 网页用图

ov5460 left bottom 网页用图

ov5460 right top 网页用图

ov5460 right bottom 网页用图

ov5460 双目组合1 网页用图

ov5460 双目组合2 网页用图

Supports up to 5 megapixels（2592×1944），compatible with multiple resolution formats
Built-in ISP (Image Signal Processor) ，supports autofocus, automatic exposure control, automatic white balance and color correction
Provides 8-bit parallel digital video interface
Supports multiple output formats including RAW RGB, YUV, JPEG, etc.
Provides two lead-out methods: FPC and 2.54mm pin/female headers

原理图 && 手册

OV5640-SCH.pdf

引脚描述

Pin	name	Description
1	GND	GND
2	VIN	Input power (5V)
3	SIOC	SCCB Clock Line
4	VSYNC	Vertical Sync Output Signal
5	SIOD	SCCB Data Line
6	HREF	Horizontal Sync Output Signal
7	D0	Bit 0 of the 8-bit output data bus
8	RESET	Hardware reset input signal
9	D2	Bit 2 of the 8-bit output data bus
10	D1	Bit 1 of the 8-bit output data bus
11	D4	Bit 4 of the 8-bit output data bus
12	D3	Bit 3 of the 8-bit output data bus
13	D6	Bit 6 of the 8-bit output data bus
14	D5	Bit 5 of the 8-bit output data bus
15	PCLK	Pixel Clock Output Signal
16	D7	Bit 7 of the 8-bit output data bus
17	PWDN	Power-down input signal
18	XLCK	24MHz clock output signal

Pin	name	Description
1~2	VIN	Input power (5V)
3~4	GND	GND
5	D2	Bit 2 of the 8-bit output data bus
6	D1	Bit 1 of the 8-bit output data bus
7	D3	Bit 3 of the 8-bit output data bus
8	D0	Bit 0 of the 8-bit output data bus
9	D4	Bit 4 of the 8-bit output data bus
10	PCLK	Pixel Clock Output Signal
11	D5	Bit 5 of the 8-bit output data bus
12	D6	Bit 6 of the 8-bit output data bus
13	XLCK	24MHz clock output signal
14	D7	Bit 7 of the 8-bit output data bus
15	HREF	Horizontal Sync Output Signal
16	PWDN	Power-down input signal
17	VSYNC	Vertical Sync Output Signal
18	RESET	Hardware reset input signal
19	SIOC	SCCB Clock Line
20	SIOD	SCCB Data Line