AXI_GPIO Expanding EMIO

Create Vivado Project

Since this project requires controlling multiple LEDs on the PL side through the PS side's EMIO, and the ZYNQ IP core we created has a maximum of 64 EMIO pins, which is insufficient for our needs, we will achieve this by adding two AXI_GPIO IPs to the existing project:

Click "+", search for "axi_gpio":

Double-click to configure: We need to configure 87 LEDs, so we need to add two IP cores. For the first IP core, select both channels and set the GPIO width to the maximum value of 32. For the second IP core, select only one channel and set the GPIO width to 23.

After configuration is complete, click "Run Connection Automation" for automatic wiring:

In the pop-up window, check all the boxes:

Constrain the GPIO pins according to the schematic:

Finally, export the hardware project .xsa file following the previous steps.

Create Vitis Project

Since the .xsa file has been updated, it needs to be updated in the Vitis project: select the exported .xsa file, and after a successful update, right-click on "Mind-Z7020" and select Build.

Similarly, in Vitis, click File-->new-->Appiacation Project:

Select a blank .c file:

After the application project is created, create a new .c file: right-click on src->New->File:

Compile and Debug

After the project is successfully compiled, connect the development board's JTAG to the computer using a Type-C USB cable.