IIC EEPROM Test

Vivado Project

Modify the hardware configuration based on the hello world Vivado project.

Modify Parameters

Click "Open Block Design". This will open the bd file created by the Hello World project:

Based on the hello_world project, you only need to add the IIC configuration. (EMIO: Used to extend the I/O functionality of the FPGA, enabling it to connect and communicate with external devices. It allows the FPGA to interact with external low-speed I/O devices through the PS section.)

Select the correct pin constraints according to the core board and baseboard schematics:

Click OK.

Right-click on IIC_0 and click Make External. The software will automatically generate external pins corresponding to the IIC_0 interface in the top-level module:

Press the shortcut Ctrl+S to save the current design. Next, click the button indicated by the arrow in the figure below to validate the current design. After validation is complete, a dialog box will pop up indicating no errors or critical warnings. Click "OK", as shown below:

Generate the top-level file: In the Sources window, select sysetm.bd under Design Sources. This is the Block Design we just completed. Right-click on sysetm.bd, and in the pop-up menu, click "Reset Output Products" and then "Generate Output Products":

In the "Hierarchy" tab, right-click on system.bd again, and then select "Create HDL Wrapper":

Run Synthesis

Click Run Synthesis, then click OK:

After it succeeds, a dialog box will pop up. Select the second option:

The interface will look like this after opening:

Since we are using EMIO, we need to add pin constraints. There are two methods to do this:

• Method 1: Add pin constraints as code in the .xdc file:

  Since this file is not generated automatically, we need to create it manually:

  • Click Constraints Wizard. In the pop-up window, click Define Target:

    

  • Click Create File:

    

  • Enter a name, click OK, then select it and click OK again:

    

    

  • The .xdc constraints file has now been created. Open the file and add the constraint statements according to the schematic mentioned earlier:

    

• Method 2: Use the GUI to select options:

  After clicking Constraints Wizard, click Cancel in the pop-up window. Options will then appear at the bottom of the interface. Select the correct Package Pin according to the schematic. A "default" warning appears because the voltage is incorrect; change it to LVCMOS33:

Run Implementation

Click Run Implementation, then click Yes. The prompt indicates that when design file changes invalidate the previous synthesis results, the tool will ask the user whether to re-run synthesis. After synthesis is complete, it will automatically proceed to the implementation step.

Because we added constraints, the results of the previous Run Synthesis step have changed. A pop-up will appear:

Click to save the constraints file:

Click OK:

Selecting the middle option will skip directly to the next step: generating the bitstream file:

Generate Bitstream

After the bitstream file is successfully generated, click Cancel:

Generate a New .xsa File

Click File->Export->Export Hardware:

Select the second option, Include bitstream:

Open Vitis and Update the .xsa File

Right-click the created platform project and click Update Hardware Specification. Select the path to the .xsa file. The following dialog box will appear. Click OK, which indicates a successful update. It is good practice to right-click the platform project and Build it again after the update.

Create a New Application Project on the Platform Project

To create a new application project on the existing platform project, refer to the creation of the hello world project. The only difference is selecting "Empty Application(C)" as the template. We need to write the code manually because the software does not provide a template for this project:

After creation, right-click Src->new->file:

For the specific code, see the files under the src directory.

For a specific implementation, you can refer to the example projects included with Vitis:

Compile and Debug

After the project is compiled successfully, connect the development board's JTAG to the computer using a Type-C USB cable. Use another Type-C USB cable to connect the board's PS UART to the computer.

Open a serial debugging tool like MobaXterm on your computer and establish a connection with the development board's PS UART.

Enter debug mode in Vitis: Under Debug As, select the first option. Run at full speed to see the debug information through the serial port.

The debugging results are as follows：