CAN Communication Test

Create a Vivado Project

Add parameter configurations to the existing hardware platform based on the schematic:

Previously created projects used PS UART0 to print debugging information. The development board also has a PL UART. This UART is converted to a USB interface by a USB-to-serial chip (CH340X) connected to the PL side pins (BANK35). The PS-side UART1 can be extended to these two PL-side pins via EMIO. This time, we will use this serial port to output debugging information.

CAN is also extended to the PL-side pins B35_IO0 and B35_IO25 via EMIO.

UART1 schematic: UART1 is extended to the PL-side pins B35_L20_P and B35_L20_N via EMIO.

Configuration interface:

On the clock configuration page, you can configure the CAN clock. This clock will be needed later for configuring the CAN baud rate and sample point.

Click OK. Similarly, right-click on CAN_0 and UART_1_0, then click 'Make External'. The software will automatically generate external pins corresponding to the CAN_0 and UART_1_0 interfaces in the top-level module. Proceed with the subsequent operations:

Configuration interface after completion based on the schematic:

After synthesis, implementation, and bitstream generation, export the new .xsa file.

Create a Vitis Project

Update the platform project in Vitis: Right-click the created platform project, click 'Update Hardware Specification', and select the .xsa file path. When the following dialog box appears, click OK, which indicates a successful update.

Since we will be using UART1 via EMIO to print debugging information, and the platform defaults to using UART0, we need to modify some platform information, specifically the BSP settings:

Similarly, although there are two Board Support Packages, you must modify the one shown below. Modifying the other one will have no effect. Finally, click OK.

Open Board Support Package -> Modify BSP Settings -> standalone and change ps7_uart_0 to ps7_uart_1. This will assign the standard input/output serial port to PS UART1.

Code implementation:

Then, rebuild the platform project.

Next, create the application project. The only difference is to select an empty .c file when choosing a template.

Add the source code from the example we provide to the project. You can also refer to the built-in test projects in Vitis. The typical path is in the Vitis installation directory: Xilinx\Vitis\2021.1\data\embeddedsw\XilinxProcessorIPLib\drivers.

CAN Baud Rate and Sample Point Configuration

Configuring the CAN baud rate on the ZYNQ7020 is done by setting the CAN controller registers. Specifically, you need to calculate and set the values for the CAN_BTR0 and CAN_BTR1 registers to achieve the desired baud rate and sample point.

Here are the detailed steps and explanations:

Determine the required baud rate and sample point:

First, you need to specify the required CAN baud rate, for example, 500 kbps or 1 Mbps. At the same time, you also need to determine the sample point, which is typically recommended to be set around 85%.

Regarding the sample point configuration, the recommendations from CiA (CAN in Automation) are as follows: (1) Generally, configure it between 75% and 80%. (2) It is optimal to select a sample point position around 85%. (3) Baud rate > 800K: 75%; Baud rate > 500K: 80%; Baud rate <= 500K: 87.5%

The baud rate and sample point configurations both require calculations based on the diagram below.

Sync Segment: Synchronization Segment (sync_seg) Propagation Segment: Propagation Time Segment (prop_seg) Phase Segment 1: Phase Buffer Segment 1 (phase_seg1) Phase Segment 2: Phase Buffer Segment 2 (phase_seg2)

Calculate the values for the BTR0 and BTR1 registers:

According to the CAN controller's technical manual, the relationship between the baud rate, sample point, and the BTR0 and BTR1 registers is as follows:

• Formulas:

  Baud Rate Calculation: Bit Rate = Fpclk / ( (1+BRP) * (1 + (1+TSEG1) + (1+ TSEG2) )

  Sample Point Calculation: SamplePoint = (sync_seg + prop_seg + phase_seg1) / (sync_seg + prop_seg + phase_seg1 + phase_seg2) * 100%

• Where:

  • Fpclk is the CAN controller clock frequency.

  • BRP is the lower 8 bits of the CAN_BTR0 register, controlling the prescaler value.

  • TSEG1 and TSEG2 are the corresponding bits in the CAN_BTR1 register, controlling the length of Time Segment 1 and Time Segment 2.

• Sample Point: The sample point is usually expressed as a percentage, for example, 87.5%. It represents the position of the sample point within a bit time, relative to the total bit time.

• Example: If Fpclk is 50 MHz, the target baud rate is 500 kbps, and the sample point is 87.5%, you can calculate BRP = 2, TSEG1 = 12, and TSEG2 = 3. The corresponding register values are CAN_BTR0 = 0x02 and CAN_BTR1 = 0x13.

Configure the CAN controller registers:

In the ZYNQ7020's CAN controller, locate the corresponding registers and write the calculated values to CAN_BTR0 and CAN_BTR1.

Start the CAN controller:

After completing the register configuration, you need to start the CAN controller to put it into an operational state.

Compile and Debug

Follow the compilation and debugging steps from the IIC documentation.

Note that the USB serial port connected to the computer should be the PL_UART on the development board this time.

CAN communication testing typically requires at least two independent CAN channels, one as the transmitter (Tx) and the other as the receiver (Rx), to verify the complete data transmission and reception functionality. The current development board has only a single CAN channel, so it cannot directly perform a self-transmitting, self-receiving test. A separate CAN device is required.

If you do not have a separate CAN device, you can only perform a loopback test:

The debugging results in loopback mode are as follows:

If you have another CAN device, you can perform a test in normal mode.

If you are using two of our development boards on a single computer and debugging the CAN communication on both boards via their JTAG ports using two separate Vitis instances, you first need to configure the JTAG ports.

Debugging Two Development Boards Simultaneously on One Computer

By default, the JTAG emulator's port is 3121. If two emulators are to be connected to their respective development boards, you need to assign different ports to each emulator.

​x
# The default emulator port is 127.0.0.1:3121, so you need to assign different ports to different emulators.
# 1. Query the emulator's JTAG port.
# Execute the following commands in the Xilinx Software Command Line Tool.
connect
jtag ta

# This will list all JTAG devices, yielding two JTAG ports: 0ABC01 and 0ABC00.
#1 my vendor co my board 0ABC01
# 2 arm_dap (idcode 4ba00477 irlen 4)
# 3 xc7z020 (idcode 23727093 irlen 6 fpga)
#4 vtino vtino board 0ABC00
# 5 arm_dap (idcode 4ba00477 irlen 4)
# 6 xc7z020 (idcode 23727093 irlen 6 fpga)
# Bind 0ABC01 to port 3121 and 0ABC00 to port 3122 by executing the following commands.
hw_server -s tcp::3121 -e "set jtag-port-filter 0ABC01" # This line is optional because the default port is 3121.
# Open another command window and execute the following command:
hw_server -s tcp::3122 -e "set jtag-port-filter 0ABC00"
# After executing the above commands, do not close the two command windows.

# If you need to rebind the ports later, you may need to release the corresponding ports first.
netstat -ano | findstr :3121 # Query the PID occupying the port.
# The query result is as follows:
# TCP 0.0.0.0:3121 0.0.0.0:0 LISTENING 10564

tasklist | findstr 10564 # Find the task.
# The result is as follows; then, kill the corresponding task in the Task Manager.
# hw_server.exe 16864 Console 6 23,652 K

Then, in Vitis, configure the respective projects to use the corresponding ports.

When debugging, select the corresponding port service